The invention relates to a push-pull output circuit in which current channels of a first and a second output transistor are connected between a first power supply terminal and an output terminal and between the output terminal and a second power supply terminal, respectively, the first output transistor being a p-type transistor, a first and a second input terminal being coupled to a control electrode of the first and the second output transistor, respectively, which input terminals receive a logic input signal and the inverse thereof, respectively.
A circuit of the kind set forth is known from European Patent Specification No. 0 171 266, which describes a push-pull output circuit in which the output transistors are of mutually different conductivity types. In the case of a voltage difference which exceeds a value U.sub.STRESS across the main electrodes of an n-type transistor, a substantial risk of so-called hot carrier stress arises because of the resultant field strength near the first main electrode. As the lengths of the current channels decrease, the value U.sub.STRESS, being the maximum voltage to prevent hot carrier stress in n-type transistors, also decreases. The value U.sub.STRESS depends not only on the length of the current channel but also on the steepness of the doping profiles of the implanted regions forming the input and output regions of a transistor, steeper doping profiles implying a reduction of the value U.sub.STRESS.
In integrated circuits in which channel lengths of transistors amount to approximately 1 .mu.m or less than 1 .mu.m (sub-micron), the doping profiles of the input and output regions of transistors are steep in order to enable still the realization of current channels between the input and output regions. In an integrated circuit in which mainly submicron transistors are implemented preferably the same process technology is used for the realization of transistors having channel lengths greater than 1 .mu.m, so that additional process steps or separate masks which usually have a cost-increasing effect can be dispensed with. For transistors having channel lengths in excess of 1 .mu.m this means that the input and output regions also have steep doping profiles, implying a small value U.sub.STRESS.
The circuit described in the cited Patent Specification has the drawback that hot carrier stress can occur in n-type transistors in the case of channel lengths which are approximately equal to or smaller than 1 .mu.m, but also in n-type transistors produced in a submicron process without additional steps or operations with channel lengths in excess of 1 .mu.m when a standard supply voltage of, for example 5 V is used Decreasing the supply voltage of the said circuit to, for example 3.3 V would preclude hot carrier stress, but would also lead to a switching speed of the output circuit which is lower than desirable.